1. Field of the Invention
This invention relates to the execution of data processing instructions.
2. Description of the Prior Art
Some data processors comprise a central processor unit (CPU) which is able, under the control of a currently executed data processing instruction, to access data stored in a random access memory (RAM) via an intermediate memory management unit. A previously proposed example of such a data processor is the ARM6 processor, described in the "ARM6 Data Sheet" published by Advanced Risc Machines Limited, 1993.
During a memory access, the memory management unit may generate an abort signal indicating that the current memory access cannot be completed. Abort signals may be generated for a number of reasons. In one example, an aborted memory access can occur in a data processing system employing virtual memory in which data are swapped between a RAM and slower disk storage to give the illusion that the addressable memory space is greater than the amount of RAM provided. In such a system, if data corresponding to a required virtual address are currently held in the disk storage rather than the RAM, there will be a delay before those data are accessible, during which delay the data have to be transferred from the disk storage into the RAM. In this case, the current memory access is aborted, and an attempt is made later to access those data.
The abort signal supplied from the memory management unit is generated too late to stop execution of the instruction which initiated the failed memory access, but can instead be used to cancel execution of the following data processing instruction, i.e. the data processing instruction after the one which initiated the failed memory access. This is useful because subsequent instructions may rely on the memory access having been successful.
The use of the abort signal to cancel execution of the instruction immediately following the instruction which initiated the failed memory access places stringent requirements on the timing of the abort signal. Alternatively, a complex mechanism must be provided to `undo` the results of the execution of the immediately following instruction, after execution of that instruction has been completed.
FIG. 1 of the accompanying drawings is a schematic timing diagram illustrating the timing requirements of the abort signal during a data write operation (in which data are written to RAM) by the previously proposed data processor referred to above.
Referring to FIG. 1, a clock signal 10 controls the execution of data processing instructions by the data processor. When a data write operation is initiated, a memory address 20 is supplied by the data processor to a memory management unit, and one half-cycle of the clock signal later, the data 30 to be written to that address are output by the data processor.
If the memory management unit detects that the memory address 20 is invalid (for example, because data corresponding to that address are currently held in disk storage in a virtual memory system), an abort signal 40 is generated by the memory management unit and supplied to the data processor.
The next instruction after a data write instruction is executed straight away, since there is no need (under normal circumstances) to await a response from the memory management unit after the data to be written have been placed on the data bus. Accordingly, in order for the abort signal to arrive in time to cancel execution of the immediately following instruction, the previously proposed data processor referred to above requires the abort signal to be valid one half-cycle of the clock signal before the data to be written are output by the data processor.
In practice, this timing constraint is difficult to achieve, and requires particularly fast operation of the memory management unit (with a correspondingly high power consumption by that unit).
The previously proposed data processor referred to above also provides conditional execution of its entire instruction set. This is achieved by comparing the current state of up to four processing flags with respective states defined by a condition code included in each instruction. This comparison takes place concurrently with execution of the instruction. Complete execution of an instruction is then prevented if the state of the processing flags does not match that specified by the condition code.
Another document describing this type of data processor is the article "ARM 6: A High Performance Low Power Consumption Macrocell", M. Muller, COMPCON Spring 93, pages 80-87. This describes the memory abort and conditional instruction execution features of the ARM 6 processor referred to above.